diff --git a/src/hardfault.rs b/src/hardfault.rs
line changes: +48/-1
index 1525891..c12b9a5
--- a/src/hardfault.rs
+++ b/src/hardfault.rs

@@ -4,7 +4,7 @@ use cortex_m::peripheral::SCB;
 
 use crate::console::flush;
 use crate::kprintf;
-use crate::task::{TaskRegisters, with_task_manager};
+use crate::task::{with_task_manager, TaskRegisters};
 
 fn print_regs(regs: &TaskRegisters) {
     kprintf!(

@@ -53,6 +53,50 @@ unsafe fn print_stack(regs: &TaskRegisters) {
     }
 }
 
+unsafe fn print_mpu() {
+    let p = doa_hallonbrod::pac::Peripherals::steal();
+    let ctrl = p.PPB.mpu_ctrl.read();
+    kprintf!(
+        "MPU_CTRL: ENABLE: {}, HFIMENA: {}, PRIVDEFENA: {}\r\n",
+        ctrl.enable().bit(),
+        ctrl.hfnmiena().bit(),
+        ctrl.privdefena().bit(),
+    );
+    for i in 0..8 {
+        p.PPB.mpu_rnr.write(|w| w.region().bits(i));
+        let rbar = p.PPB.mpu_rbar.read();
+        let rasr = p.PPB.mpu_rasr.read();
+        kprintf!("MPU Region {} ", i);
+        if rasr.enable().bit() {
+            let attrs = rasr.attrs().bits();
+            kprintf!(
+                "ENABLED addr {:08X} size {:08X} srd {:08b} TEXSCB {:06b} {}",
+                rbar.addr().bits() << 8,
+                2_u32.pow(rasr.size().bits() as u32 + 1),
+                rasr.srd().bits(),
+                attrs & 0b111111,
+                match (attrs >> 8) & 0b111 {
+                    0b000 => "none/none",
+                    0b001 => "RW/none",
+                    0b010 => "RW/RO",
+                    0b011 => "RW/RW",
+                    0b100 => "RESERVED",
+                    0b101 => "RO/none",
+                    0b110 => "RO/RO (110)",
+                    0b111 => "RO/RO (111)",
+                    _ => unreachable!(),
+                }
+            );
+            if attrs & (1 << 12) != 0 {
+                kprintf!(" XN");
+            }
+        } else {
+            kprintf!("DISABLED");
+        }
+        kprintf!("\r\n");
+    }
+}
+
 // This one is slightly different than the usual ExceptionEntry/Exit
 // because we want to know the registers even if we came from handler
 // mode.

@@ -113,6 +157,9 @@ unsafe fn hardfault_handler(regs: &mut TaskRegisters, thread_mode: bool) {
     print_stack(regs);
     kprintf!("\r\n");
 
+    print_mpu();
+    kprintf!("\r\n");
+
     let scb = &(*cortex_m::peripheral::SCB::PTR);
     kprintf!("ICSR: {:08X}\r\n", scb.icsr.read());
     flush();

diff --git a/src/mpu.rs b/src/mpu.rs
line changes: +1/-1
index 2b41ff5..ea6f1f9
--- a/src/mpu.rs
+++ b/src/mpu.rs

@@ -65,7 +65,7 @@ impl MemorySegment {
     }
 
     pub fn as_region(&self) -> MemoryRegion {
-        //let subregions = !(!(0xFF << self.size) << self.page);
+        //let subregions = !(!(0xFF << self.size) << (self.page % 8));
         let subregions = 0;
         MemoryRegion {
             start: self.start_address(),