diff --git a/test/tb.gtkw b/test/tb.gtkw
line changes: +5/-5
index dc7492e..5e517c7
--- a/test/tb.gtkw
+++ b/test/tb.gtkw

@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Thu Aug 29 04:46:09 2024
+[*] Thu Aug 29 06:05:28 2024
 [*]
 [dumpfile] "/home/chip/projects/tinytapeout/munch/test/tb.vcd"
-[dumpfile_mtime] "Thu Aug 29 04:39:17 2024"
-[dumpfile_size] 163326
+[dumpfile_mtime] "Thu Aug 29 06:02:53 2024"
+[dumpfile_size] 625482
 [savefile] "/home/chip/projects/tinytapeout/munch/test/tb.gtkw"
-[timestart] 0
+[timestart] 10000000
 [size] 1711 925
 [pos] -1 -1
-*-17.534531 120000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-16.534531 120000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] tb.
 [sst_width] 297
 [signals_width] 229

diff --git a/test/tb.v b/test/tb.v
line changes: +21/-9
index ac70cdb..974f280
--- a/test/tb.v
+++ b/test/tb.v

@@ -1,6 +1,9 @@
 `default_nettype none
 `timescale 1ns / 1ps
 
+/* This testbench just instantiates the module and makes some convenient wires
+   that can be driven / tested by the cocotb test.py.
+*/
 module tb ();
 
   // Dump the signals to a VCD file. You can view it with gtkwave.

@@ -13,19 +16,28 @@ module tb ();
   // Wire up the inputs and outputs:
   reg clk;
   reg rst_n;
+  reg ena;
+  reg [7:0] ui_in;
+  reg [7:0] uio_in;
   wire [7:0] uo_out;
   wire [7:0] uio_out;
   wire [7:0] uio_oe;
 
-  tt_um_bytex64_munch munch(
-    .clk(clk),
-    .rst_n(rst_n),
-    .ena(1'b1),
-    .ui_in(8'b0),
-    .uo_out(uo_out),
-    .uio_in(8'b0),
-    .uio_out(uio_out),
-    .uio_oe(uio_oe)
+  // Replace tt_um_example with your module name:
+  tt_um_bytex64_munch user_project(
+      // Include power ports for the Gate Level test:
+`ifdef GL_TEST
+      .VPWR(1'b1),
+      .VGND(1'b0),
+`endif
+      .ui_in  (ui_in),    // Dedicated inputs
+      .uo_out (uo_out),   // Dedicated outputs
+      .uio_in (uio_in),   // IOs: Input path
+      .uio_out(uio_out),  // IOs: Output path
+      .uio_oe (uio_oe),   // IOs: Enable path (active high: 0=input, 1=output)
+      .ena    (ena),      // enable - goes high when design is selected
+      .clk    (clk),      // clock
+      .rst_n  (rst_n)     // not reset
   );
 
 endmodule

diff --git a/test/test.py b/test/test.py
line changes: +7/-1
index 7c62fa1..fb5f5f0
--- a/test/test.py
+++ b/test/test.py

@@ -11,7 +11,7 @@ async def reset(dut):
     dut.rst_n.value = 1
     await ClockCycles(dut.clk, 1);
     dut.rst_n.value = 0
-    await ClockCycles(dut.clk, 1);
+    await ClockCycles(dut.clk, 3);
     dut.rst_n.value = 1
 
 @cocotb.test()

@@ -28,10 +28,16 @@ async def test_munch(dut):
     clock = Clock(dut.clk, 40, units="ns")
     cocotb.start_soon(clock.start())
 
+    await Timer(5, "us")
+    dut.ena.value = 1
+    await Timer(5, "us")
+
     await reset(dut)
 
     dut._log.info("Test munch module")
 
+    # flops on hsync/vsync delay them by one cycle, so we wait
+    # two cycles here.
     await ClockCycles(dut.clk, 2)
     # Should be a black pixel at the beginning of scan
     assert dut.uo_out.value == 0b10001000