# Tiny Tapeout project information
project:
  title:        "Munch"      # Project title
  author:       "bytex64"      # Your name
  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
  description:  "Displays munching squares through VGA PMOD"      # One line description of what your project does
  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
  clock_hz:     25175000       # Clock frequency in Hz (or 0 if not applicable)

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_bytex64_munch"

  # List your project's source files here.
  # Source files must be in ./src and you must list each source file separately, one per line.
  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
  source_files:
    - "hvsync_generator.v"
    - "audio.v"
    - "video.v"
    - "project.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: ""
  ui[1]: ""
  ui[2]: ""
  ui[3]: ""
  ui[4]: ""
  ui[5]: ""
  ui[6]: ""
  ui[7]: ""

  # Outputs
  uo[0]: "R1"
  uo[1]: "G1"
  uo[2]: "B1"
  uo[3]: "VSYNC"
  uo[4]: "R0"
  uo[5]: "G0"
  uo[6]: "B0"
  uo[7]: "HSYNC"

  # Bidirectional pins
  uio[0]: ""
  uio[1]: ""
  uio[2]: ""
  uio[3]: ""
  uio[4]: "beat clock bit 1 (output)"
  uio[5]: "beat clock bit 2 (output)"
  uio[6]: "beat clock bit 3 (output)"
  uio[7]: "audio (output)"

# Do not change!
yaml_version: 6